DRAM.GOLD // ANALYSIS · APPENDIX
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// APPENDIX · MEMORY BOTTLENECK DRAM IS THE NEW GOLD.

Memory is one of the constraints the book asks us to follow. This companion page explores how a bottleneck can move between compute, power, memory and deployment.

the memory question — then back to the book

⚠ THE VAULT HAS BEEN BREACHED
READING LENS
HBM
bandwidth and capacity
SYSTEM QUESTION
POWER
what can be deployed?
WORKLOAD QUESTION
TOKENS
what useful work is delivered?
BOOK CONNECTION
CH. 2
the integrated architecture
DRAM IS THE NEW GOLD ◆ BANDWIDTH · CAPACITY · POWER ◆ FOLLOW THE BOTTLENECK ◆ A READING LENS, NOT A PRICE FORECAST ◆
WATCH · LISTEN · EXPLORE THREE FORMATS
[01]ONE THESIS, THREE DELIVERY SYSTEMS

Three formats. One thesis.

Video, audio, and a slide deck — for whichever way you metabolise an idea.

A READING LENS · NOT A LIVE MARKET DASHBOARDCOMPUTE / POWER / MEMORY / DEPLOYMENT
[02]THE QUESTION BEHIND THE DOMAIN

Follow the bottleneck.

Not a neat relay race in which chips stop mattering, then power stops mattering, then memory takes over. A system can run into several limits at once.

The book’s second chapter asks why an integrated architecture can be so difficult to reproduce. Memory makes the question tangible: an accelerator is useful as part of a working system, not as a performance figure detached from capacity, bandwidth, interconnects, power and software.

the chip is not the whole system.
neither is the bottleneck.— an author’s reading note

The research question is where the constraint moves for a particular workload. What limits the result now? Which improvement shifts that limit elsewhere? When does tighter integration remain valuable, and when does a more modular approach become useful?

A faster component is a possibility.
A useful system is the test.

Chapter 8 moves the same inquiry into energy and existing industrial sites. The Token Standard takes it towards accounting and the economics of useful results. Neither turn makes a token automatically correct, an action authorised, or a transaction settled.

This page keeps the original memory-related reading and media trail together. It is a companion to the April 2026 book, not a source of live memory prices, supply forecasts or investment recommendations. For dated corrections and developments, use the edition notes and the October afterword.

RESEARCH · CURATED RESOURCES DIG IN
[03]RESEARCH · CURATED RESOURCES

Three places to dig in.

Long-form analysis, investor perspective, and the running press digest on chip-and-memory geopolitics.

DISCUSS WITH AI · IN YOUR LANGUAGE EIGHT FRAMES
[04]DISCUSS WITH AI · IN YOUR LANGUAGE

Eight languages. Eight assistants.

A test of how the same argument lands across linguistic frames, measured against the assistants that already index the literature.

ESSENTIAL READING · DEEPER CONTEXT FIVE BOOKS
[05]ESSENTIAL READING · DEEPER CONTEXT

Five books that frame the conversation.

If you want the upstream literature on chip geopolitics, capital, and the structural rise of computing as a strategic resource.

The NVIDIA Innovator's Dilemma — 3D cover

// COMPANION VOLUME

The NVIDIA Innovator's Dilemma

This appendix is the memory layer of the silicon argument made in The NVIDIA Innovator's Dilemma. The book covers the chip; this page covers the bottleneck behind the chip; the companion essay covers what comes after both.

→ Read the book

the triptych is complete: the chip, the bottleneck, the token